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1、I C P l a t f o r m A-PDF Watermark DEMO: Purchase from www.A-PDF.com to remove the watermark I C P l a t f o r m Pros Cons CoC- 1st 1. Chips committed post Si interposer process 2. Better uBump joining control than CoS 1. uBump joining issue for thin interposer 2. Thin wafer handling related yield
2、loss 3. Post-uBump joint test not possible CoS- 1st 1. Chip committed LAST 2. Compatible with larger top die 3. KGD handling 1. uBump joining issue for large top die 2. Thin wafer handling related yield loss 3. Large warpage during the process CoW- 1st 1. Favorable uBump joining 2. Large die compati
3、ble 3. Avoid thin wafer handling 4. Friendly to density scaling 5. Compatible to TSV free stacking 1. Chips committed early 2. Wafer level process tool investment I C P l a t f o r m (CoW)-oS (CoC)-oS I C P l a t f o r m I C P l a t f o r m 6 No shift in TSV resistance from either processes “A” or “
4、B” after TCB stress. Process A and B are equivalent for TSVs. I C P l a t f o r m I C P l a t f o r m 8/1 start point I C P l a t f o r m I C P l a t f o r m I C P l a t f o r m 1X Die Yield1X die cost4 1X die cost4X Die Yield4X die costDie Cost Ratio2D PKG2.5D PKGDevice Cost Delta 10%5.0020.000.01%
5、20000.001000.001219979.00 25%2.008.000.39%512.0064.0012503.00 50%1.004.006.25%32.008.001227.00 63%0.793.1715.75%12.704.00128.52 79%0.632.5338.95%5.132.03121.60 99%0.512.0296.06%2.081.0312-0.94 1.00 10.00 100.00 1000.00 10%25%50%63%79%99% Die Cost Ratio (1 Die vs. 4X Die/4) with Die Yield Die Cost Ra
6、tio I C P l a t f o r m 1X Die Yield1X die cost4 1X die cost4X Die Yield4X die costDie Cost Ratio2D PKG2.5D PKGDevice Cost Delta 10%5.0020.000.01%20000.001000.001219979.00 25%2.008.000.39%512.0064.0012503.00 50%1.004.006.25%32.008.001227.00 63%0.793.1715.75%12.704.00128.52 79%0.632.5338.95%5.132.031
7、21.60 99%0.512.0296.06%2.081.0312-0.94 -5.00 0.00 5.00 10.00 15.00 20.00 25.00 30.00 50%63%79%99% Total Device Cost Delta (1 Die vs. 4X Die/4) with Die Yield Device Cost Delta with 20% wafer price reduction each step I C P l a t f o r m Source: Renesas. I C P l a t f o r m Design guidelines and soft
8、ware must be available Thermal issue: 3D IC increase total power generated per unit surface area Chips in the stack may overheat if cooling is not sufficient Space may be too small for cooling channels (very small gap for fluid flow) Thinning chips creates extreme conditions for on-chip hot spots Lo
9、w cost thermal management solutions must be developed to expand the market and applications Before Thermal Vias After Thermal Vias Source: University on Minn. I C P l a t f o r m Process Technology Structure BOM, MFG Reliability Design Methodology EDA tool Design rule Design flow Performance & Simul
10、ation Digital, RF PDN, IO System Software Expanded IP Expanded memory Timing Partitioning Supply Chain Foundry Substrate OSAT Memory, etc. Char SIPI/jitter Bandwidth Data rate System Test Fine pitch probing Thin wafer handling KGD I C P l a t f o r m Some of the new AMD Radeon R9 300 Series cards th
11、at will be coming out this year will be the first GPUs in the World that come with High Bandwidth Memory (HBM). AMD is always working on the next generation technology and AMD sees that HBM will help raise the bar when it comes to performance and help usher in the era of 4K gaming and Virtual Realit
12、y. Posted by Nathan Kirsch Wed, May 06, 2015 - 7:06 PM I C P l a t f o r m AMD has been working HBM for almost seven years as the whole supply chain needed to come together for HBM to come to market. HBM allows for an extremely fast connection as you dont have to go off chip to make that connection!
13、 This design is more compact and it requires less power. AMD says that they are seeing 50% power savings and 3x the Performance per Watt versus the GDDR5 memory implementation currently used! With the video cards memory now being on-die it frees up space versus being on the PCB. Will AMD have a solu
14、tion that will let them pull ahead of NVIDIA when it comes to 4K and VR performance and how lone will it take NVIDIA to catch up if they need to? Dr. Lisa Su gave us a little glipmse today during AMDs financial analyst day, but we want more information and of course benchmark numbers! I C P l a t f
15、o r m I C P l a t f o r m Xilinx FPGA proto shipments in 2012 Networking 2015-16 GPU 2015 Server 2016-2017 TechSearch International, Inc. I C P l a t f o r m CMOS Image sensor in HVM Memory stacks in HVM 2015, Tezzaron memory stacks earlier Logic and memory stack for mobile 2018 (at earliest) Logic
16、and logic 2019 (at earliest) Automotive image sensors for safety 2019 Source: TechSearch International, Inc. I C P l a t f o r m FPGAs since 2012 GPU with memory stack in 2015 ASIC for networking with memory stack 2015 Servers with memory stack in 2016 Tablets possible in 2018 Automotive sensors in 2019 TechSearch International, Inc. I C P l a t f o r m TSMC CoWoS Technology Top dies are attached to full-th
