dc测试原理

上传人:简****9 文档编号:101765338 上传时间:2019-09-29 格式:PDF 页数:39 大小:843.23KB
返回 下载 相关 举报
dc测试原理_第1页
第1页 / 共39页
dc测试原理_第2页
第2页 / 共39页
dc测试原理_第3页
第3页 / 共39页
dc测试原理_第4页
第4页 / 共39页
dc测试原理_第5页
第5页 / 共39页
点击查看更多>>
资源描述

《dc测试原理》由会员分享,可在线阅读,更多相关《dc测试原理(39页珍藏版)》请在金锄头文库上搜索。

1、?Top confidential?Confidential?Internal use only 页数:1 of 39 Page: 核 准:揚威 Approved by: 文件编号:KN2000307N No. 制订者:章晨杰 Initial by: 文件名称:DC測試原 Title: 制订部门:CP產品工程部 Initial Dept.: New Issue 增加DC測試Fail的Datalog案 調整“ DC測試原”內容 - 夏長山 夏長山 2000-06082 2000-08035 2008-08052 2006-10-23 2008-06-24 2008-08-14 A B C 说明

2、Description 修订者 Reviser ECN编号 ECN No. 生效日期 Effective Date 版次 Rev. 京 科 技 訓 教 材 教材編號: 京 科 技 訓 教 材 教材編號:KN2000307N 課程:課程:DC 測試原 講師:譚濤 測試原 講師:譚濤 3 Ohms Law To Calculate Resistance: R = E / I resistance (voltage divided by current) ParameterTest ConditionsMin MaxUnits of MeasurementVOL Output LOW Voltage

3、VDD = Min, IOL = 8.0mA0.4 Voltage A VOL specification can be used as an example to calculate resistance: VOL = 0.4V, IOL = 8.0mA. Example: R = E/I E = 0.4 (VOL) I = 0.008 (IOL) R =0.4/0.008R = 50 NOTE: Remember that in many cases a resistor can be used in place of the DUT to verify if a test is work

4、ing correctly. This can be a very effective debug tool. One of the main goals of debugging is to make sure the only errors are those of the DUT and not test program or load board errors. Using a resistor guarantees a good “DUT equivalent.” 4 CURRENT VOLTAGE Measure CURRENT VOLTAGE Force PMUPMU Test

5、Limits -5.2m a DUT PASS LT +2.4V VDDmin ON OFF VSS = 0V IOH Force Sense Apply VDDmin. Set Voltage Clamp Precondition output to logic 1 (output high). Using PMU,current per specification. Wait 1 to 5 msec (Set PMU delay). Measure resultant voltage. Fails VOH if measured voltage is. force IOH less tha

6、n +2.4V Output Voltage Test VOH/IOH DUT Output Pin FAIL VOH 4.3V S T Output Voltage Test 5 VDD(min) = 4.75V Actual Device Output Circuit Equivalent Circuit for Rout Calculation VDD(min) = 4.75V ON OFF ON OFF VSS = 0VVSS = 0V IOH IOH Specification IOH(min) = -5.2mA VOH(min) = 2.4V E = VDD - VOH R = E

7、 / I E= 4.75 - 2.4 = 2.35 R = 2.35 / 0.0052 R = 452(maximum) VOH/IOH Resistance Calculation DUT Output Pin E VOH S T VOH/IO H Res. Cal. 6 Datalog of: VOH/IOH Serial/Static test using the PMU Pin Force/rngMeas/rngMin Max Result PIN1 -5.2mA/ 10mA 4.30V/8V 2.40 VPASS PIN2 -2.0mA/ 10mA 2.34V/8V 2.40 VFA

8、IL PIN3 -5.2mA/ 10mA 3.96V/8V 2.40 VPASS PIN4 -5.2mA/ 10mA 3.95V/8V 2.40 VPASS PIN5 -8.0mA/ 10mA 3.85V/8V 2.40 VPASS PIN6 -8.0mA/ 10mA -0.782V/8V 2.40 VFAIL VOH Datalog 7 CURRENT VOLTAGE Measure CURRENT VOLTAGE Force PMUPMU Test Limits 8.0m A DUT FAIL VOL GT +0.4V VDDmin OFF ON VSS = 0V IOL Force Se

9、nse Apply VDDmin. Precondition output to logic 0 (output low). Set Voltage Clamp Using PMU,current per specification. Wait 1 to 5 msec (Set PMU delay). Measure resultant voltage. Fails VOL if measured voltage is. force IOL greater than +0.4V Output Voltage Test VOL/IOL DUT Output Pin PASS 0.1 5V Out

10、put Voltag e Test 8 VDD(min) = 4.75V Actual Device Output Circuit Equivalent Circuit for Rout Calculation VDD(min) = 4.75V OFFOFF ON ON VSS = 0VVSS = 0V IOL IOL E VOL Specification IOL(min) = 8.0mA VOL(max) = 0.4V R = E / I E = VOL - VSS = 0.4 R = 0.4 / 0.008 R = 50(maximum) VOL/IOL Resistance Calcu

11、lation DUT Output Pin S T VOL/ IOL Res. Cal. 9 Datalog of: VOL/IOL Serial/Static test using the PMU Pin Force/rngMeas/rngMin Max Result PIN1 12.0mA/20mA130mV/8V400mV PASS PIN2 12.0mA/20mA421mV/8V400mV FAIL PIN3 4.0mA/10mA125mV/8V400mV PASS PIN4 4.0mA/10mA90mV/8V400mV PASS PIN5 8.0mA/10mA205mV/8V400m

12、V PASS PIN6 8.0mA/10mA 5.52V/8V 400mV FAIL 10 CURRENT VOLTAGE Measure +8.7m A CURRENT VOLTAGE Force PMU or DPS PMU Test Limits 5.25VFAIL IDD FAIL IDD PASS GT IDD Limit LT -1.0mA VSS = 0V VDDmax IDD Force Sense Using DPS or PMU,. Set Maximum Current Clamp on DPS/PMU Set Pass/Fail Limits. Set all inpu

13、ts Low/High or Execute Reset Sequence. Stop pattern. Wait 5 to 10msec Measure current flowing into VDD pin(s). Fails IDD if measured current is apply VDDmax outside of limits. Gross IDD Test Vector Memory & Pin Electronics (Apply Reset Pattern) S T S T Gross IDD Test 11 Equivalent Circuit for Rin Ca

14、lculation VDD = 5.25V VSS = 0V IDD Path IDD Path Specification VDD = 5.25V IDD max = 45mA R = E / I E = VDD - VSS (= 5.25 - 0.0) R = 5.25 / 45mA R = 117 Gross IDD Resistance Calculation Device Equivalent Resistance Device DUT Power Pin(s) S T S T Gross IDD Res. Cal. 12 CURRENT VOLTAGE Measure +1 9.2

15、 A CURRENT VOLTAGE Force PMU or DPS PMU Test Limits 5.25VFAIL IDD PASS GT IDD spec VSS = 0V VDDmax IDD Using DPS or PMU,. Execute Preconditioning Pattern. Stop pattern. Wait 1 to 5msec (Set delay). Measure current flowing into VDD pin(s). Fails IDD test if measured current is. apply VDDmax greater t

16、han IDD spec Static IDD Test Vector Memory & Pin Electronics (Apply Preconditioning Pattern) S T S T 13 Equivalent Circuit for Rin Calculation VDD = 5.25V VSS = 0V IDD Path IDD Path Specification VDD = 5.25V IDD max = 22 A R = E / I E = VDD - VSS (= 5.25 - 0.0) R = 5.25 / 22 A R = 238,636 Static IDD Resistance Calculation Device Equivalent Resistance Device DUT Power Pin(s) S T S T Static IDD Res. Cal. 14 CURRENT VOLTAGE Measure +1 2.4m A CU

展开阅读全文
相关资源
正为您匹配相似的精品文档
相关搜索

最新文档


当前位置:首页 > 商业/管理/HR > 管理学资料

电脑版 |金锄头文库版权所有
经营许可证:蜀ICP备13022795号 | 川公网安备 51140202000112号