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1、Advanced Packaging Tech,Outline,Package Development Trend 3D Package WLCSP & Flip Chip Package,Package Development Trend,SO Family,QFP Family,BGA Family,Package Development Trend,CSP Family,Memory Card,SiP Module,Package Development Trend,3D Package,3D Package,3D Package Introduction,Functional Inte
2、gration,High,Low,2 Chip Stack Wirebond,2 Chip Stack Flip Chip & Wirebond,Multi Chip Stack,Package on Package (PoP) Stacking,PS-fcCSP + SCSP,Paper Thin,PiP,PoP QFN,Stacked Die,Top die,Bottom die,FOW materil,Wire,TSV,TSV (Through Silicon Via) A through-silicon via (TSV) is a vertical electrical connec
3、tion (via) passing completely through a silicon wafer or die. TSV technology is important in creating 3D packages and 3D integrated circuits. A 3D package (System in Package, Chip Stack MCM, etc.) contains two or more chips (integrated circuits) stacked vertically so that they occupy less space. In
4、most 3D packages, the stacked chips are wired together along their edges. This edge wiring slightly increases the length and width of the package and usually requires an extra “interposer” layer between the chips. In some new 3D packages, through-silicon via replace edge wiring by creating vertical
5、connections through the body of the chips. The resulting package has no added length or thickness.,Wire Bonding Stacked Die,Whats PoP? PoP is Package on Package Top and bottom packages are tested separately by device manufacturer or subcon.,PoP,PoP,PS-vfBGA,PS-etCSP,Low Loop Wire,Pin Gate Mold,Packa
6、ge Stacking,Wafer Thinning,PoP Core Technology,PoP,Allows for warpage reduction by utilizing fully-molded structure More compatible with substrate thickness reduction Provides fine pitch top package interface with thru mold via Improved board level reliability Larger die size / package size ratio Co
7、mpatible with flip chip, wire bond, or stacked die configurations Cost effective compared to alternative next generation solutions,Amkors TMV PoP,PoP,Ball Placement on top surface,Ball Placement on bottom,Die Bond,Mold (Under Full optional),Laser drilling,Singulation Final Visual Inspection,Base Mtl
8、,Thermal effect,Process Flow of TMV PoP,Digital(Btm die) + Analog(Middle die) + Memory(Top pkg) Potable Digital Gadget Cellular Phone, Digital Still Camera, Potable Game Unit,Memory die,Analog die,Digital die,spacer,Epoxy,PiP,Easy system integration Flexible memory configuration 100% memory KGD Thin
9、ner package than POP High IO interconnection than POP Small footprint in CSP format,It has standard ball size and pitch,Constructed with: Film Adhesive die attach Epoxy paste for Top PKG Au wire bonding for interconnection Mold encapsulation,Why PiP?,PiP,Material for High Reliability Based on Low Wa
10、rpage,Wafer Thinning,Fine Process Control Top Package Attach Die Attach etc,Optimized Package Design,Flip Chip,Under-fill,Top epoxy,ISM,PiP Core Technology,PiP,Analog,WB PIP,FC PIP,PiP,PiP W/B PiP and FC PiP,WLCSP & Flip Chip Package,WLCSP,What is WLCSP? WLCSP(Wafer Level Chip Scale Packaging), is n
11、ot same as traditional packaging method (dicing packaging testing, package size is at least 20% increased compared to die size). WLCSP is packaging and testing on wafer base, and dicing later. So the package size is exactly same as bare die size. WLCSP can make ultra small package size, and high ele
12、ctrical performance because of the short interconnection.,WLCSP,Why WLCSP? Smallest package size: WLCSP have the smallest package size against die size. So it has widely use in mobile devices. High electrical performance: because of the short and thick trace routing in RDL, it gives high SI and redu
13、ced IR drop. High thermal performance: since there is no plastic or ceramic molding cap, heat from die can easily spread out. Low cost: no need substrate, only one time testing. WLCSPs disadvantage Because of the die size and pin pitch limitation, IO quantity is limited (usually less than 50pins). B
14、ecause of the RDL, stagger IO is not allowed for WLCSP.,RDL,RDL: Redistribution Layer A redistribution layer (RDL) is a set of traces built up on a wafers active surface to re-route the bond pads. This is done to increase the spacing between each interconnection(bump).,WLCSP,Process Flow of WLCSP,WL
15、CSP,Process Flow of WLCSP,Flip Chip Package,FCBGA (Passive Integrated Flip Chip BGA),(PI)-EHS-FCBGA (Passive Integrated Exposed Heat Sink Flip Chip BGA),(PI)-EHS2-FCBGA (Passive Integrated Exposed 2 pieces of Heat Sink Flip Chip BGA),MCM-FCBGA (Multi-Chip-Module FCBGA),PI-EHS-MP-FCBGA (Passive Integ
16、rated Exposed Heat Sink Multi Package Flip Chip),Bump,Bump Development,Bump Development,Bump Development,C4 Flip Chip,Whats C4 Flip Chip? C4 is: Controlled Collapsed Chip Connection Chip is connected to substrate by RDL and Bump Bump material type: solder, gold,C4 Flip Chip BGA,Main Features Ball Pitch:0.4mm - 1.27mm Package size: up to 55mmx55mm Substrate layer: 4-16 Layers Ball
